EOS/ESD and Latchup IC Failures

The information below has been carefully extracted from the past approximately 7 years of cooperation with a total of 17 companies worldwide (IDMs, fabless design houses, foundry) in EOS/ESD and latchup projects. The data involves 38 ICs with mostly one ESD failure issue (approx. 2/3rd of the cases) while ther other chips encountered multiple ESD failures. Slightly more than half of the products include automotive or/and high-voltage IC applications.

According to QPX history, about 85% of all EOS/ESD troubleshooting projects did NOT require any new ESD device! 

ic_esdfail_stat_opt

Please find below more details for the different categories of diagnosed and fixed EOS/ESD issues:

Category-1 ESD issues: Interconnect and ESD placement (>50%)

  • Violation of ESD design window (mainly due to interconnect issues)
  • Too high effective metal resistance (e.g. of busses)
  • Metal bottleneck (e.g. for high ESD demands)
  • ESD protection element applied at wrong IC node
  • Wrong ESD protection element applied at right IC node
  • Inappropriate ESD protection arrangement, e.g. incorrect ESD referencing
  • Missing ESD protection elements (i.e. available in library but not placed)
  • Wrong ESD resistor, capacitor design
  • Interconnect sparking (e.g. for ultra-high ESD demands)
  • etc
  • No IP or ESD testchip development required to fix category-1 issues

Category-2 ESD issues: Existing ESD Device & Circuit Fix (approx. 30%)

  • Flaw in ESD device design, e.g. issues in metal wiring within structure, multi-finger arrangement, device layout dimension / spacing, device head, termination
  • Flaw in ESD circuit design, e.g. trigger circuit, inter-device parasitics, wrong resistive elements 
  • Insufficient or non-functional (transient) latchup design pre-cautions
  • Measures as described in category-1 may be required additionally
  • No IP or ESD testchip development required to fix category-2 issues

Category-3 ESD issues: Different ESD Architecture/Topology  (approx. 16%)

  • A cause of customer returns of malfunctioning ICs is missing signal integrity ( caused by e.g. a too low ESD trigger current), or an EMC issues (caused by e.g. a too high RC constant for ESD detection in dynamic clamps), or an EOS failure (caused by e.g. too low Vhold < Vsupply). These issues result in a fatal wrong triggering of the ESD protection during normal operation conditions (e.g. due to fast IO signal slew rate, IC power-up conditions, latch-up events, system-level disturbances). In this case, the original ESD device may need to replaced by a different reliable ESD protection solution.
  • Entirely different ESD device architecture required to resolve ESD protection (e.g. more effective clamping required) or normal operation issue as described above
  • Entirely different ESD circuit topology required, e.g. changing the circuit of an active clamp for low RC
  • Measures as described in category-1/-2 may be required additionally
  • IP and/or testchip development needed
  • This category includes also a few cases where the entire IC floorplan, bus, and pad-ring architecture did not allow for fixing the ESD issue without any signficant IC re-design mainly at the peripherie.

In conclusion, this means: In about 85% of all IC troubleshooting cases, NO new ESD device is required! Often, the ESD elements itself is not the problem but the ESD protection arrangement or the metal wiring or there is simply something missing. If your ESD device or circuit does not work the way you want it to work, a (layout) tweak may repair it. The ESD architecture may be alright with a flawed layout implementation.

If an entirely new ESD device or circuit is required to resolve the IC ESD problems, chances are high, that it can be designed based on expired prior-art patents or based on public domain ESD, or QPX solutions.

 

What makes it hard for a non-expert to identify the root cause of EOS/ESD or latchup failure?

Among other shortcomings, there seems to be a pattern for ESD inexperienced IC experts to resolve a complex ESD issue on IC-level:

„The IC failure site usually does not coincide with the IC ESD design issue! And failure spot is where non-experts tend to focus on  …

 

Why customers usually come to us for support?

  • No resources?
  • No time?
  • No expert?
  • No confidence?
  • No idea?
  • No solution?